双栅极(FinFET)和三栅极mosfet:仿真和设计

A. Breed, K. Roenker
{"title":"双栅极(FinFET)和三栅极mosfet:仿真和设计","authors":"A. Breed, K. Roenker","doi":"10.1109/ISDRS.2003.1272037","DOIUrl":null,"url":null,"abstract":"The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace the conventional planar MOSFET. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. However, the physics of the MOSFET's operation in these new device structures is somewhat different. This study aims to investigate the differences in performance of these two devices and their device design using a commercial, three-dimensional numerical simulator ATLAS from Silvaco International.","PeriodicalId":369241,"journal":{"name":"International Semiconductor Device Research Symposium, 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Dual-gate (FinFET) and tri-Gate MOSFETs: simulation and design\",\"authors\":\"A. Breed, K. Roenker\",\"doi\":\"10.1109/ISDRS.2003.1272037\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace the conventional planar MOSFET. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. However, the physics of the MOSFET's operation in these new device structures is somewhat different. This study aims to investigate the differences in performance of these two devices and their device design using a commercial, three-dimensional numerical simulator ATLAS from Silvaco International.\",\"PeriodicalId\":369241,\"journal\":{\"name\":\"International Semiconductor Device Research Symposium, 2003\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Semiconductor Device Research Symposium, 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISDRS.2003.1272037\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Semiconductor Device Research Symposium, 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISDRS.2003.1272037","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14

摘要

硅MOSFET器件尺寸持续缩小到十分之一微米以下,为未来的集成电路应用提出了新的严峻挑战。因此,人们提出了新的MOSFET结构,如双栅极(FinFET)和三栅极晶体管,以取代传统的平面MOSFET。这些器件与传统的硅集成电路工艺兼容,但当器件缩放到纳米范围时,提供了卓越的性能。然而,在这些新的器件结构中,MOSFET工作的物理原理有些不同。本研究旨在利用来自Silvaco International的商用三维数值模拟器ATLAS来研究这两种器件的性能差异及其器件设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Dual-gate (FinFET) and tri-Gate MOSFETs: simulation and design
The continued downward scaling of silicon MOSFET device dimensions below one tenth micron has presented new and serious challenges for future integrated circuit applications. Accordingly, new MOSFET structures, such as the dual-gate (FinFET) and the tri-Gate transistor, have been proposed to replace the conventional planar MOSFET. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. However, the physics of the MOSFET's operation in these new device structures is somewhat different. This study aims to investigate the differences in performance of these two devices and their device design using a commercial, three-dimensional numerical simulator ATLAS from Silvaco International.
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