Barra: GPGPU的并行功能模拟器

2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems Pub Date : 2010-08-17 DOI:10.1109/MASCOTS.2010.43

Caroline Collange, M. Daumas, D. Defour, David Parello

{"title":"Barra: GPGPU的并行功能模拟器","authors":"Caroline Collange, M. Daumas, D. Defour, David Parello","doi":"10.1109/MASCOTS.2010.43","DOIUrl":null,"url":null,"abstract":"We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the native instruction set of the Tesla architecture at the functional level. The inputs are CUDA executables produced by NVIDIA tools. No alterations are needed to perform simulations. As it uses parallelism, Barra generates detailed statistics on executions in about the time needed by CUDA to operate in emulation mode. We use it to understand and explore the micro-architecture design spaces of GPUs.","PeriodicalId":406889,"journal":{"name":"2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"119","resultStr":"{\"title\":\"Barra: A Parallel Functional Simulator for GPGPU\",\"authors\":\"Caroline Collange, M. Daumas, D. Defour, David Parello\",\"doi\":\"10.1109/MASCOTS.2010.43\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the native instruction set of the Tesla architecture at the functional level. The inputs are CUDA executables produced by NVIDIA tools. No alterations are needed to perform simulations. As it uses parallelism, Barra generates detailed statistics on executions in about the time needed by CUDA to operate in emulation mode. We use it to understand and explore the micro-architecture design spaces of GPUs.\",\"PeriodicalId\":406889,\"journal\":{\"name\":\"2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-08-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"119\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MASCOTS.2010.43\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MASCOTS.2010.43","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 119

摘要

我们介绍了Barra，一个图形处理单元(GPU)模拟器，用于通用处理(GPGPU)。它基于UNISIM框架，在功能层面模拟了Tesla架构的本地指令集。输入是由NVIDIA工具生成的CUDA可执行文件。执行模拟不需要任何更改。由于它使用并行性，Barra在CUDA在仿真模式下运行所需的时间内生成有关执行的详细统计数据。我们用它来理解和探索gpu的微架构设计空间。

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Barra: A Parallel Functional Simulator for GPGPU

We present Barra, a simulator of Graphics Processing Units (GPU) tuned for general purpose processing (GPGPU). It is based on the UNISIM framework and it simulates the native instruction set of the Tesla architecture at the functional level. The inputs are CUDA executables produced by NVIDIA tools. No alterations are needed to perform simulations. As it uses parallelism, Barra generates detailed statistics on executions in about the time needed by CUDA to operate in emulation mode. We use it to understand and explore the micro-architecture design spaces of GPUs.

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2010 IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems

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