{"title":"一种采用模拟正弦转换技术的低功耗直接数字频率合成器","authors":"Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu","doi":"10.1109/ISLPED.2011.5993635","DOIUrl":null,"url":null,"abstract":"A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock frequency, the power consumption is 50 mw at 1. 8-V power supply and the spurious free dynamic range (SFDR) is 44 dBc at the N yquist synthesized frequency. The total chip area is 0.52 mm2.","PeriodicalId":117694,"journal":{"name":"IEEE/ACM International Symposium on Low Power Electronics and Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique\",\"authors\":\"Jun-Hong Weng, Ching-Yuan Yang, Yi-Lin Jhu\",\"doi\":\"10.1109/ISLPED.2011.5993635\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock frequency, the power consumption is 50 mw at 1. 8-V power supply and the spurious free dynamic range (SFDR) is 44 dBc at the N yquist synthesized frequency. The total chip area is 0.52 mm2.\",\"PeriodicalId\":117694,\"journal\":{\"name\":\"IEEE/ACM International Symposium on Low Power Electronics and Design\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE/ACM International Symposium on Low Power Electronics and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISLPED.2011.5993635\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/ACM International Symposium on Low Power Electronics and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISLPED.2011.5993635","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low-power direct digital frequency synthesizer using an analogue-sine-conversion technique
A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock frequency, the power consumption is 50 mw at 1. 8-V power supply and the spurious free dynamic range (SFDR) is 44 dBc at the N yquist synthesized frequency. The total chip area is 0.52 mm2.
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