{"title":"基于fpga设计的高效小波图像编码器","authors":"M. Lanuzza, S. Perri, P. Corsonello, G. Cocorullo","doi":"10.1109/SIPS.2005.1579946","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a new wavelet-based encoder suitable for fast and low-power image and video compression. The proposed circuit is based on a modified version of the No List SPIHT algorithm. When realized using a XILINX Virtex XC2V1000 device, the new encoder requires only 3.4 ms to perform lossless image compression on a 128/spl times/128 16-bit discrete wavelet transformed image. It uses 392 slices, /spl sim/15 KB of RAM memory and dissipates just 8.2 mW/MHz.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"An efficient wavelet image encoder for FPGA-based designs\",\"authors\":\"M. Lanuzza, S. Perri, P. Corsonello, G. Cocorullo\",\"doi\":\"10.1109/SIPS.2005.1579946\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a new wavelet-based encoder suitable for fast and low-power image and video compression. The proposed circuit is based on a modified version of the No List SPIHT algorithm. When realized using a XILINX Virtex XC2V1000 device, the new encoder requires only 3.4 ms to perform lossless image compression on a 128/spl times/128 16-bit discrete wavelet transformed image. It uses 392 slices, /spl sim/15 KB of RAM memory and dissipates just 8.2 mW/MHz.\",\"PeriodicalId\":436123,\"journal\":{\"name\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2005.1579946\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2005.1579946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient wavelet image encoder for FPGA-based designs
This paper presents the design of a new wavelet-based encoder suitable for fast and low-power image and video compression. The proposed circuit is based on a modified version of the No List SPIHT algorithm. When realized using a XILINX Virtex XC2V1000 device, the new encoder requires only 3.4 ms to perform lossless image compression on a 128/spl times/128 16-bit discrete wavelet transformed image. It uses 392 slices, /spl sim/15 KB of RAM memory and dissipates just 8.2 mW/MHz.