Impact of Design Parameter on SRAM Bit Cell

SRAM Bit-Cell Sleep technique is widely used in processors to reduce SRAM leakage power. However, significance of leakage power savings from SRAM bit-cell sleep technique is dependent on process technology and various design parameters. This paper evaluates the effects of design parameters like ITD, DVS and VDCMIN_RET on performance of 7T SRAM bit-cell sleep technique. Impact of Process Technology on SRAM bit-cell sleep technique performance, due to transition from silicon dioxide (SIO2) to Hafnium based High-K gate dielectric material is also discussed in this paper. Hafnium is a chemical element and found in zirconium minerals, its atomic number is 72. Silicon measurement results of a 3MegaByte SRAM array designed in 45 nm High-K CMOS process is used to demonstrate reducing effectiveness of SRAM bit-cell sleep technique.