Nanomilling and STEM Imaging of Sub-50 nm InP HEMT

The sub-50 nm Indium Arsenide Composite Channel (IACC) High Electron Mobility Transistors (HEMTs) are fabricated on 100 mm Indium Phosphide (InP) substrates. This technology offers the best performance for low-noise and high-frequency, space and military applications. Typical failure mechanisms are observed in III-V HEMT technologies, including gate sinking, impact ionization and electromigration. Experiments were conducted to understand failure mechanisms of the IACC HEMTs by life testing devices at accelerated temperatures and biases; their electrical characteristics were measured at each stress interval. In order to determine which devices and where any defects occurred after the accelerated life tests, an additional test was completed, a Low-Noise Amplifier (LNA) Circuit assessment. The Low-Noise Amplifier (LNA) Circuit assessment determines which HEMT device is the weakest amongst the LNA circuit. Since many of the known III-V semiconductor failure mechanisms physically degrade or damage HEMTs, cross-sections are important to prepare to detect these mechanisms. In this presentation, advanced microscopy techniques with sub-nanometer resolutions, will examine physical characteristics of the HEMT at the atomic scale. The microscopy techniques will include a Focused Ion Beam/Scanning Electron Microscope (FIB/SEM), Nanomill and a Transmission Electron Microscope (TEM) along with Energy Dispersive Spectroscopy (EDS).