{"title":"0.9 v双平衡正交输入正交输出分频器","authors":"Hui Zheng, H. Luong","doi":"10.1109/CICC.2006.320959","DOIUrl":null,"url":null,"abstract":"A double-balanced quadrature-input quadrature-output (QIQO) divider is proposed. By making use of the quadrature phase outputs from a quadrature VCO (QVCO) or the other quadrature signal generator, the proposed QIQO divider provides a mechanism to achieve an output IQ phase sequence that is inherently tracked with the input IQ phase sequence. Moreover, compared with conventional dividers, the QIQO divider not only provides smaller and better-matched input loading to the QVCO but also improved quadrature phase accuracy for both QVCO and the divider itself. Fabricated in a 0.18-mum CMOS process and operated at 0.9 V, the QIQO divider measures an image rejection of -62 dBc while consuming 7.2 mW","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"21 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider\",\"authors\":\"Hui Zheng, H. Luong\",\"doi\":\"10.1109/CICC.2006.320959\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A double-balanced quadrature-input quadrature-output (QIQO) divider is proposed. By making use of the quadrature phase outputs from a quadrature VCO (QVCO) or the other quadrature signal generator, the proposed QIQO divider provides a mechanism to achieve an output IQ phase sequence that is inherently tracked with the input IQ phase sequence. Moreover, compared with conventional dividers, the QIQO divider not only provides smaller and better-matched input loading to the QVCO but also improved quadrature phase accuracy for both QVCO and the divider itself. Fabricated in a 0.18-mum CMOS process and operated at 0.9 V, the QIQO divider measures an image rejection of -62 dBc while consuming 7.2 mW\",\"PeriodicalId\":269854,\"journal\":{\"name\":\"IEEE Custom Integrated Circuits Conference 2006\",\"volume\":\"21 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Custom Integrated Circuits Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2006.320959\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Custom Integrated Circuits Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2006.320959","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
提出了一种双平衡正交输入、正交输出(QIQO)分压器。通过利用来自正交VCO (QVCO)或其他正交信号发生器的正交相位输出,所提出的QIQO分频器提供了一种机制,以实现与输入IQ相序列固有跟踪的输出IQ相序列。此外,与传统分频器相比,QIQO分频器不仅为QVCO提供了更小、更匹配的输入负载,而且提高了QVCO和分频器本身的正交相位精度。QIQO分压器采用0.18 μ m CMOS工艺,工作电压为0.9 V,图像抑制为-62 dBc,功耗为7.2 mW
A 0.9-V Double-Balanced Quadrature-Input Quadrature-Output Frequency Divider
A double-balanced quadrature-input quadrature-output (QIQO) divider is proposed. By making use of the quadrature phase outputs from a quadrature VCO (QVCO) or the other quadrature signal generator, the proposed QIQO divider provides a mechanism to achieve an output IQ phase sequence that is inherently tracked with the input IQ phase sequence. Moreover, compared with conventional dividers, the QIQO divider not only provides smaller and better-matched input loading to the QVCO but also improved quadrature phase accuracy for both QVCO and the divider itself. Fabricated in a 0.18-mum CMOS process and operated at 0.9 V, the QIQO divider measures an image rejection of -62 dBc while consuming 7.2 mW