{"title":"近程FMCW应用中基于FPGA频率的实时SAR图像处理的发展与潜力","authors":"M. Pfitzner, F. Cholewa, P. Pirsch, H. Blume","doi":"10.1109/RADAR.2013.6651968","DOIUrl":null,"url":null,"abstract":"This paper presents the potential of standard frequency domain based SAR image generation techniques for real-time short-range FMCW applications. Exemplarily, a Range-Doppler algorithm is implemented in hardware and evaluated for a 80 GHz, 25 GHz bandwidth FMCW system. For implementation a hardware-in-the-loop framework is presented, capable of coupling high-level MATLAB code with different hardware evaluation environments. This allows for a gradual swap of time-critical signal processing tasks from software to hardware. The stepwise swap makes a precise analysis of discrete algorithmic stages possible, leading to an optimized hardware description. A dramatic increase of computation speed can be observed compared to time domain based image generation techniques.","PeriodicalId":365285,"journal":{"name":"2013 International Conference on Radar","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Development and potential of real-time FPGA frequency-based SAR image processing for short-range FMCW applications\",\"authors\":\"M. Pfitzner, F. Cholewa, P. Pirsch, H. Blume\",\"doi\":\"10.1109/RADAR.2013.6651968\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the potential of standard frequency domain based SAR image generation techniques for real-time short-range FMCW applications. Exemplarily, a Range-Doppler algorithm is implemented in hardware and evaluated for a 80 GHz, 25 GHz bandwidth FMCW system. For implementation a hardware-in-the-loop framework is presented, capable of coupling high-level MATLAB code with different hardware evaluation environments. This allows for a gradual swap of time-critical signal processing tasks from software to hardware. The stepwise swap makes a precise analysis of discrete algorithmic stages possible, leading to an optimized hardware description. A dramatic increase of computation speed can be observed compared to time domain based image generation techniques.\",\"PeriodicalId\":365285,\"journal\":{\"name\":\"2013 International Conference on Radar\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 International Conference on Radar\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RADAR.2013.6651968\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 International Conference on Radar","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADAR.2013.6651968","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Development and potential of real-time FPGA frequency-based SAR image processing for short-range FMCW applications
This paper presents the potential of standard frequency domain based SAR image generation techniques for real-time short-range FMCW applications. Exemplarily, a Range-Doppler algorithm is implemented in hardware and evaluated for a 80 GHz, 25 GHz bandwidth FMCW system. For implementation a hardware-in-the-loop framework is presented, capable of coupling high-level MATLAB code with different hardware evaluation environments. This allows for a gradual swap of time-critical signal processing tasks from software to hardware. The stepwise swap makes a precise analysis of discrete algorithmic stages possible, leading to an optimized hardware description. A dramatic increase of computation speed can be observed compared to time domain based image generation techniques.