{"title":"可编程协议处理器的一种灵活的寄存器访问控制","authors":"Y. Ma, A. Jantsch, H. Tenhunen","doi":"10.1109/MWSCAS.2001.986209","DOIUrl":null,"url":null,"abstract":"We investigate a programmable processor architecture for internet protocol processing and use IP packet forward as a case study. We focus on flexible register access capability to support packet analysis and encapsulation. Compared to general-purpose superscalar microprocessors, our architecture achieves at least a two-fold improvement in performance.","PeriodicalId":403026,"journal":{"name":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A flexible register access control for programmable protocol processors\",\"authors\":\"Y. Ma, A. Jantsch, H. Tenhunen\",\"doi\":\"10.1109/MWSCAS.2001.986209\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We investigate a programmable processor architecture for internet protocol processing and use IP packet forward as a case study. We focus on flexible register access capability to support packet analysis and encapsulation. Compared to general-purpose superscalar microprocessors, our architecture achieves at least a two-fold improvement in performance.\",\"PeriodicalId\":403026,\"journal\":{\"name\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-08-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2001.986209\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2001.986209","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A flexible register access control for programmable protocol processors
We investigate a programmable processor architecture for internet protocol processing and use IP packet forward as a case study. We focus on flexible register access capability to support packet analysis and encapsulation. Compared to general-purpose superscalar microprocessors, our architecture achieves at least a two-fold improvement in performance.