高并行处理器中l触发的失效分析

2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515) Pub Date : 2003-12-01 DOI:10.1109/NSSMIC.2003.1351928

G. Cancelo, E. Gottschalk, V. Pavlicek, M. Wang, J. Wu

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引用次数: 0

摘要

本文研究了在费米实验室的Tevatron上运行的BTeV实验中，处理器故障如何影响一级触发器的数据流。对于一个拥有超过2500个处理节点和许多相同数量级的存储单元和通信链路的系统，故障分析是至关重要的。故障分析基于L1触发器体系结构的模型，并显示了体系结构数据流的动态。故障分析可以深入了解单个组件故障如何影响系统变量，并为错误恢复策略的实现提供关键信息。该分析既包括短期故障(系统可以从中快速恢复)，也包括长期故障(意味着更剧烈的错误恢复策略)。建模结果得到了L1触发器处理BTeV大蒙特卡罗数据的行为模拟的支持。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Failure Analysis in a highly parallel processor for Ll Triggering

The current paper studies how processor failures affect the dataflow of the Level I Trigger in the BTeV experiment proposed to run at Fermilab's Tevatron. The failure analysis is crucial for a system with over 2500 processing nodes and a number of storage units and communication links of the same order of magnitude. The failure analysis is based on models of the L1 Trigger architecture and shows the dynamics of the architecture's dataflow. The failure analysis provides insight into how system variables are affected by single component failures and provides key information to the implementation Of error recovery strategies. The analysis includes both short term failures from which the system can recover quickly and long term failures which imply a more drastic error recovery strategy. The modeling results are supported by behavioral simulations of the L1 Trigger processing BTeV's Geant Monte Carlo data.

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2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515)

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