Design of an SoC Based on 32-bit RISC-V CPU and Lightweight Block Cipher PRINCE on FPGA

This paper discusses an SoC consisting of the algorithm of PRINCE, a block cipher used in lightweight cryptography, and a 32-bit RISC-V CPU. The system was implemented successfully on an Intel DE2-115 FPGA board. The PRINCE core was functionally validated using a simulation waveform on ModelSim and an embedded Nios II processor on Intel's FPGA. The PRINCE core was integrated with 32-bit RISC-V to form a custom SoC on an FPGA. The SoC utilizes 8,127 logic elements, 2,983 registers, 391,872 memory bits, eight multipliers, and one PLL block. The proposed SoC based on the open-source 32-bit RISC-V CPU and the lightweight cryptography core, which were implemented on FPGA, consumed fewer logic resources. It can be used to design a secure SoC system or a compact Trusted Execution Environment suitable for Internet of Things security systems.