C-GEP: 100 Gbit/s的、基于fpga的、可重构的网络设备

P. Varga, László Kovács, Tamás Tóthfalusi, P. Orosz
{"title":"C-GEP: 100 Gbit/s的、基于fpga的、可重构的网络设备","authors":"P. Varga, László Kovács, Tamás Tóthfalusi, P. Orosz","doi":"10.1109/HPSR.2015.7483084","DOIUrl":null,"url":null,"abstract":"Programmable networking platforms are in the spotlight since the advent of SDN (Software Defined Networking). It is a great challenge to create such a platform - especially with reconfigurable hardware and line-rate capabilities reaching and exceeding 100 Gbit/s. These requirements together put FPGA (Field Programmable Gate Array) technology into the focus of high performance networking. In this paper, we introduce a highly flexible, programmable, multi-purpose networking platform, which is capable of hosting multiple 1 and 10 Gbit/s Ethernet interfaces - beside their 40 or 100 Gbit/s interface. The hardware of the introduced C-GEP platform is reconfigurable, even on-the-fly; due to the FPGA technology. C-GEP can host a wide range of high-speed network specific applications - including monitoring, switching and media conversion -, and it is aligned with the SDN principles. The system consists of two main building blocks: a high performance FPGA-based custom specific hardware platform and the firmware tailored to the actual task. The architecture is briefly introduced by its hardware and firmware setup, then some of the core functionalities, such as packet processing, filtering, and switching are presented.","PeriodicalId":360703,"journal":{"name":"2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"C-GEP: 100 Gbit/s capable, FPGA-based, reconfigurable networking equipment\",\"authors\":\"P. Varga, László Kovács, Tamás Tóthfalusi, P. Orosz\",\"doi\":\"10.1109/HPSR.2015.7483084\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Programmable networking platforms are in the spotlight since the advent of SDN (Software Defined Networking). It is a great challenge to create such a platform - especially with reconfigurable hardware and line-rate capabilities reaching and exceeding 100 Gbit/s. These requirements together put FPGA (Field Programmable Gate Array) technology into the focus of high performance networking. In this paper, we introduce a highly flexible, programmable, multi-purpose networking platform, which is capable of hosting multiple 1 and 10 Gbit/s Ethernet interfaces - beside their 40 or 100 Gbit/s interface. The hardware of the introduced C-GEP platform is reconfigurable, even on-the-fly; due to the FPGA technology. C-GEP can host a wide range of high-speed network specific applications - including monitoring, switching and media conversion -, and it is aligned with the SDN principles. The system consists of two main building blocks: a high performance FPGA-based custom specific hardware platform and the firmware tailored to the actual task. The architecture is briefly introduced by its hardware and firmware setup, then some of the core functionalities, such as packet processing, filtering, and switching are presented.\",\"PeriodicalId\":360703,\"journal\":{\"name\":\"2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR)\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HPSR.2015.7483084\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 16th International Conference on High Performance Switching and Routing (HPSR)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPSR.2015.7483084","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15

摘要

自SDN(软件定义网络)出现以来,可编程网络平台一直备受关注。创建这样一个平台是一个巨大的挑战——特别是在可重构硬件和达到并超过100 Gbit/s的线路速率能力的情况下。这些要求共同使FPGA(现场可编程门阵列)技术成为高性能网络的焦点。在本文中,我们介绍了一个高度灵活,可编程,多用途的网络平台,它能够承载多个1和10 Gbit/s以太网接口-除了他们的40或100 Gbit/s接口。引入的C-GEP平台的硬件是可重构的,即使是在运行中;由于FPGA技术。C-GEP可以承载广泛的高速网络特定应用,包括监控、交换和媒体转换,并且它符合SDN原则。该系统由两个主要构建块组成:基于高性能fpga的定制特定硬件平台和针对实际任务量身定制的固件。通过硬件和固件设置简要介绍了该体系结构,然后介绍了一些核心功能,如包处理、过滤和交换。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
C-GEP: 100 Gbit/s capable, FPGA-based, reconfigurable networking equipment
Programmable networking platforms are in the spotlight since the advent of SDN (Software Defined Networking). It is a great challenge to create such a platform - especially with reconfigurable hardware and line-rate capabilities reaching and exceeding 100 Gbit/s. These requirements together put FPGA (Field Programmable Gate Array) technology into the focus of high performance networking. In this paper, we introduce a highly flexible, programmable, multi-purpose networking platform, which is capable of hosting multiple 1 and 10 Gbit/s Ethernet interfaces - beside their 40 or 100 Gbit/s interface. The hardware of the introduced C-GEP platform is reconfigurable, even on-the-fly; due to the FPGA technology. C-GEP can host a wide range of high-speed network specific applications - including monitoring, switching and media conversion -, and it is aligned with the SDN principles. The system consists of two main building blocks: a high performance FPGA-based custom specific hardware platform and the firmware tailored to the actual task. The architecture is briefly introduced by its hardware and firmware setup, then some of the core functionalities, such as packet processing, filtering, and switching are presented.
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