{"title":"一个10ns双极存储器，与18 I/O总线工作","authors":"D. Omet","doi":"10.1109/ESSCIRC.1980.5468766","DOIUrl":null,"url":null,"abstract":"A double 576 bits random access memory organized as 2×32 words by 18 bits has been designed, completely tested, and qualified from a functionality and reliability point of view. The two major advantages of this memory are a good speedpower trade off for this particular type of organization and its ability to work with two independant 18 bits I/O busses.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 10ns Bipolar Memory, Working with 18 I/O Bus\",\"authors\":\"D. Omet\",\"doi\":\"10.1109/ESSCIRC.1980.5468766\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A double 576 bits random access memory organized as 2×32 words by 18 bits has been designed, completely tested, and qualified from a functionality and reliability point of view. The two major advantages of this memory are a good speedpower trade off for this particular type of organization and its ability to work with two independant 18 bits I/O busses.\",\"PeriodicalId\":168272,\"journal\":{\"name\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1980-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1980.5468766\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 80: 6th European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1980.5468766","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A double 576 bits random access memory organized as 2×32 words by 18 bits has been designed, completely tested, and qualified from a functionality and reliability point of view. The two major advantages of this memory are a good speedpower trade off for this particular type of organization and its ability to work with two independant 18 bits I/O busses.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
