{"title":"高速逻辑和存储器的接口","authors":"S. Schuster, N. Lu","doi":"10.1109/VLSIC.1993.920554","DOIUrl":null,"url":null,"abstract":"Summary form only given. Rapid advances in technology and design have resulted in microprocessors with greater than 200 MHz clock rates and several hundred I/O. In this high speed environment the reliable transmission of signals between logic and memory is a fundamental requirement.The problem is further exacerbated by the widening gap between processor and memory performance.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Interfacing of high speed logic and memory\",\"authors\":\"S. Schuster, N. Lu\",\"doi\":\"10.1109/VLSIC.1993.920554\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. Rapid advances in technology and design have resulted in microprocessors with greater than 200 MHz clock rates and several hundred I/O. In this high speed environment the reliable transmission of signals between logic and memory is a fundamental requirement.The problem is further exacerbated by the widening gap between processor and memory performance.\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920554\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920554","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Summary form only given. Rapid advances in technology and design have resulted in microprocessors with greater than 200 MHz clock rates and several hundred I/O. In this high speed environment the reliable transmission of signals between logic and memory is a fundamental requirement.The problem is further exacerbated by the widening gap between processor and memory performance.
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