一个1.8 V 14 b 10 MS/s的流水线ADC, 0.18 /spl mu/m CMOS, 99db SFDR

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332792

Y. Chiu, Paul R. Gray, Borivoje Nikolic

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引用次数: 22

摘要

采用无源电容误差平均和嵌套CMOS增益提升的1.8 V, 14 b流水线ADC在信号频率高达5.1 MHz时实现99 dB SFDR，无需修整或校准。在1 MHz模拟输入下，DNL为0.31 LSB, INL为0.58 LSB, SNDR为73.6 dB。该芯片在0.18 /spl mu/m CMOS中占用15 mm/sup / 2/，功耗为112 mW。

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A 1.8 V 14 b 10 MS/s pipelined ADC in 0.18 /spl mu/m CMOS with 99 dB SFDR

A 1.8 V, 14 b pipelined ADC using passive capacitor error-averaging and nested CMOS gain boosting achieves 99 dB SFDR for signal frequencies up to 5.1 MHz without trimming or calibration. With a 1 MHz analog input, DNL is 0.31 LSB, INL is 0.58 LSB, and SNDR is 73.6 dB. The chip occupies 15 mm/sup 2/ in 0.18 /spl mu/m CMOS and dissipates 112 mW.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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