Design of novel reversible logic gate with enhanced traits

A reversible logic gate is a functional unit with a one-to-one mapping between inputs and outputs. A unique output vector is produced by the reversible circuit for each input vector. In this paper, a new reversible logic gate called G1 is proposed. A set of benchmark circuit is implemented using the proposed G1. The proposed design is better in terms of count of reversible gates, garbage outputs, constant inputs, quantum cost and delay when compared with the existing circuits. The design is simulated in Xilinx 14.7 Spartan 3E platform. The work has been done for making the design optimal in terms of count of reversible gates, garbage outputs, constant inputs and quantum cost.