An improved & optimized layer assignment partitioning algorithm: For upcoming 3D VLSI shrinking technologies

The advancement of technology has led to an exceptional demand for high speed VLSI architectures having huge structures and high complexity. System partitioning provides an easy approach to recursively split the whole system into small sub-systems called blocks. With the enormous increase of system complexity in the past and further advancement of microelectronic system design, partitioning has become a central and sometimes critical design task. With the shrinking technology, interconnect dominates the chip performance and to reduce the number of interconnections between blocks is the biggest challenge for a designer. The 3D technology seems to significantly aid the reduction of wire length and also dealing with the issues like delay, power dissipation and signal integrity etc. In this work, an improved solution for layer assignment problem has been proposed utilizing the concept of adjacency matrix of a graph. It optimizes and reduces the complexity of already existing algorithm based on the concept of adjacency matrix of a graph. The final results prove the efficiency of the proposed method over existing works.