Design of a 4-bit 1.4 Gsamples/s low power folding ADC for DS-CDMA UWB transceivers

In this paper, we present a CMOS low power folding ADC (analog to digital converter) architecture, which takes advantage of the low resolution requirement of DS-CDMA UWB transceivers to reduce the power consumption. The high sampling rate is achieved by adopting current steering folding amplifiers instead of cross coupled differential pair based folding amplifiers. Our ADC adopts both resistive interpolation and multiplication to fold the input signal, thereby, reducing the number of folding amplifiers required. When this technique is applied to higher resolution converters, the power and area savings will be even more significant. A brief analysis on the operation of the folding amplifier and a systematic method for sizing preamplifiers, folding amplifiers and comparators is presented. The ADC has been designed in 0.13 /spl mu/m IBM CMOS process. Post layout simulation shows that the spurious free dynamic range (SFDR) of our ADC is greater than 24 dB up to 540 MHz at 1.4 GS/s and consumes about 62 mW of power. The results also indicate that the proposed architecture consumes less power and achieves a higher sampling rate than existing folding ADCs.