Implementation of Combinational Logic for Polar Decoder

Error free communication is possible due to channel coding. Polar code has been identified by control channel code for 5G wireless communication. In this paper we implement combinational logic for polar decoder. As compare to sequential circuits for polar decoder, the proposed combinational logic circuit has low complexity in design. The parallel architecture of proposed logic provides fastest logic for the designing of polar decoder. Polar decoder by using sequential bit decoding approach is also proposed here. The design implementation and its simulations are done on Xilinx platform using Verilog HDL. The analysis for complexity and delay is done here.