{"title":"基于FPGA的H.264/AVC运动估计模块硬件成本优化","authors":"Gaoming Du, Mingliang He, Y. Song, Duoli Zhang","doi":"10.1109/ICIST.2013.6747793","DOIUrl":null,"url":null,"abstract":"H.264/AVC has excellent compression efficiency and network-friendly design, but it gets the advanced performance at the expense of highly complex calculation, resulting in huge hardware cost, especially motion estimation (ME) module. To reduce the logic resource consumption (LRC) without any obvious increase of the bit-rate, this paper simplifies the calculation of the block matching parameter with replaced pixel-bits and replaced pixels, and discusses how the LRC of ME module and the bit-rate are affected by the number of replaced bits and replaced pixels for different video motion scenes based on FPGA. The experimental results show three reasonable optimization approaches, in which the ratio of bit-rate increment is less than 0.47% and the LRC drops 24% to 45% compared with full search (FS) algorithm.","PeriodicalId":415759,"journal":{"name":"2013 IEEE Third International Conference on Information Science and Technology (ICIST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Optimizing hardware cost of motion estimation module for H.264/AVC based on FPGA\",\"authors\":\"Gaoming Du, Mingliang He, Y. Song, Duoli Zhang\",\"doi\":\"10.1109/ICIST.2013.6747793\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"H.264/AVC has excellent compression efficiency and network-friendly design, but it gets the advanced performance at the expense of highly complex calculation, resulting in huge hardware cost, especially motion estimation (ME) module. To reduce the logic resource consumption (LRC) without any obvious increase of the bit-rate, this paper simplifies the calculation of the block matching parameter with replaced pixel-bits and replaced pixels, and discusses how the LRC of ME module and the bit-rate are affected by the number of replaced bits and replaced pixels for different video motion scenes based on FPGA. The experimental results show three reasonable optimization approaches, in which the ratio of bit-rate increment is less than 0.47% and the LRC drops 24% to 45% compared with full search (FS) algorithm.\",\"PeriodicalId\":415759,\"journal\":{\"name\":\"2013 IEEE Third International Conference on Information Science and Technology (ICIST)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-03-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Third International Conference on Information Science and Technology (ICIST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIST.2013.6747793\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Third International Conference on Information Science and Technology (ICIST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIST.2013.6747793","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimizing hardware cost of motion estimation module for H.264/AVC based on FPGA
H.264/AVC has excellent compression efficiency and network-friendly design, but it gets the advanced performance at the expense of highly complex calculation, resulting in huge hardware cost, especially motion estimation (ME) module. To reduce the logic resource consumption (LRC) without any obvious increase of the bit-rate, this paper simplifies the calculation of the block matching parameter with replaced pixel-bits and replaced pixels, and discusses how the LRC of ME module and the bit-rate are affected by the number of replaced bits and replaced pixels for different video motion scenes based on FPGA. The experimental results show three reasonable optimization approaches, in which the ratio of bit-rate increment is less than 0.47% and the LRC drops 24% to 45% compared with full search (FS) algorithm.