基于FPGA的H.264/AVC运动估计模块硬件成本优化

Gaoming Du, Mingliang He, Y. Song, Duoli Zhang
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引用次数: 0

摘要

H.264/AVC具有出色的压缩效率和网络友好的设计,但它以高度复杂的计算为代价获得了先进的性能,导致了巨大的硬件成本,尤其是运动估计(ME)模块。为了在比特率没有明显提高的情况下降低逻辑资源消耗(LRC),本文采用替换的像素位和替换的像素简化了块匹配参数的计算,并讨论了基于FPGA的不同视频运动场景下ME模块的LRC和比特率受替换比特数和替换像素数的影响。实验结果表明,采用三种合理的优化方法,比特率增量比小于0.47%,LRC比全搜索(FS)算法下降24% ~ 45%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimizing hardware cost of motion estimation module for H.264/AVC based on FPGA
H.264/AVC has excellent compression efficiency and network-friendly design, but it gets the advanced performance at the expense of highly complex calculation, resulting in huge hardware cost, especially motion estimation (ME) module. To reduce the logic resource consumption (LRC) without any obvious increase of the bit-rate, this paper simplifies the calculation of the block matching parameter with replaced pixel-bits and replaced pixels, and discusses how the LRC of ME module and the bit-rate are affected by the number of replaced bits and replaced pixels for different video motion scenes based on FPGA. The experimental results show three reasonable optimization approaches, in which the ratio of bit-rate increment is less than 0.47% and the LRC drops 24% to 45% compared with full search (FS) algorithm.
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