软件定义硬件的动态可配置网络

2020 IEEE High Performance Extreme Computing Conference (HPEC) Pub Date : 2020-09-22 DOI:10.1109/HPEC43674.2020.9286148

William Butera

{"title":"软件定义硬件的动态可配置网络","authors":"William Butera","doi":"10.1109/HPEC43674.2020.9286148","DOIUrl":null,"url":null,"abstract":"This paper describes an on-die network architecture targeted for Software-Defined Hardware (SDH). Key performance goals are near ASIC-level performance over a wide range of communication patterns, dynamically configured for operation on tile arrays with O(104) tiles and defect densities in excess of 10%. We describe a network architecture based on two recent Intel circuit studies, and present simulator results that demonstrate extremes for configurability, scale-invariant place & route and resilience to defect","PeriodicalId":168544,"journal":{"name":"2020 IEEE High Performance Extreme Computing Conference (HPEC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Dynamically Configurable Network for Software-Defined Hardware\",\"authors\":\"William Butera\",\"doi\":\"10.1109/HPEC43674.2020.9286148\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes an on-die network architecture targeted for Software-Defined Hardware (SDH). Key performance goals are near ASIC-level performance over a wide range of communication patterns, dynamically configured for operation on tile arrays with O(104) tiles and defect densities in excess of 10%. We describe a network architecture based on two recent Intel circuit studies, and present simulator results that demonstrate extremes for configurability, scale-invariant place & route and resilience to defect\",\"PeriodicalId\":168544,\"journal\":{\"name\":\"2020 IEEE High Performance Extreme Computing Conference (HPEC)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-09-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE High Performance Extreme Computing Conference (HPEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HPEC43674.2020.9286148\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE High Performance Extreme Computing Conference (HPEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPEC43674.2020.9286148","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文描述了一种针对软件定义硬件(SDH)的片上网络架构。关键性能目标是在广泛的通信模式下接近asic级别的性能，动态配置在0(104)瓦片和缺陷密度超过10%的瓦片阵列上运行。我们基于最近的两项英特尔电路研究描述了一种网络架构，并给出了模拟结果，证明了可配置性、规模不变的位置和路由以及对缺陷的弹性

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Dynamically Configurable Network for Software-Defined Hardware

This paper describes an on-die network architecture targeted for Software-Defined Hardware (SDH). Key performance goals are near ASIC-level performance over a wide range of communication patterns, dynamically configured for operation on tile arrays with O(104) tiles and defect densities in excess of 10%. We describe a network architecture based on two recent Intel circuit studies, and present simulator results that demonstrate extremes for configurability, scale-invariant place & route and resilience to defect

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2020 IEEE High Performance Extreme Computing Conference (HPEC)

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