{"title":"用于90nm CMOS掩模光刻接口的6b DAC和模拟DRAM","authors":"D. Fang, R. Roberts, B. Nikolić","doi":"10.1109/ASSCC.2006.357941","DOIUrl":null,"url":null,"abstract":"A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS\",\"authors\":\"D. Fang, R. Roberts, B. Nikolić\",\"doi\":\"10.1109/ASSCC.2006.357941\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2006.357941\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357941","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
一种并联、12 μ m间距、低功耗6-b分段数模转换器(DAC)阵列在2.5/1 V 90nm CMOS工艺中驱动3 μ m x 3 μ m模拟DRAM单元阵列，应用于无掩模光刻。创新的自校准补偿电路将电荷泄漏和电容过程失配的影响限制在100 ms数据保持时间内小于0.5 LSB。一个2mm × 2mm的测试芯片实现了一个混合信号接口，32个dac驱动4个32 × 256模拟DRAM阵列。
A 6-b DAC and Analog DRAM for a Maskiess Lithography Interface in 90 nm CMOS
A parallel, 12 mum-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3 mum x 3 mum analog DRAM cells in a 2.5/1 V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5 LSB over 100 ms of data hold time. A 2 mm x 2 mm test chip implements a mixed-signal interface with 32 DACs driving four 32 times 256 analog DRAM arrays.
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