物理dft中不可检测的非反馈短段的研究

R. McGowen, F. Ferguson
{"title":"物理dft中不可检测的非反馈短段的研究","authors":"R. McGowen, F. Ferguson","doi":"10.1109/EDTC.1994.326849","DOIUrl":null,"url":null,"abstract":"Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise or delay, or increase test pattern generation costs. This paper describes the undetectable nonfeedback shorts that are likely to occur in standard cell implementations of the ISCAS'85 combinational test circuits. For ten layouts of each circuit, all shorts between adjacent wires were extracted and the undetectable ones analyzed. We found that approximately 0.4% are undetectable and that nearly half of these can be easily predicted before the physical layout of the circuit is generated. Since only a small percentage of the shorts are undetectable, and many of the undetectables are easily identifiable, it appears that it is possible to reduce the likelihood, or completely eliminate, the occurrence of a large portion of these shorts by incorporating design-for-test strategies into routing software.<<ETX>>","PeriodicalId":244297,"journal":{"name":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A study of undetectable non-feedback shorts for the purpose of physical-DFT\",\"authors\":\"R. McGowen, F. Ferguson\",\"doi\":\"10.1109/EDTC.1994.326849\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise or delay, or increase test pattern generation costs. This paper describes the undetectable nonfeedback shorts that are likely to occur in standard cell implementations of the ISCAS'85 combinational test circuits. For ten layouts of each circuit, all shorts between adjacent wires were extracted and the undetectable ones analyzed. We found that approximately 0.4% are undetectable and that nearly half of these can be easily predicted before the physical layout of the circuit is generated. Since only a small percentage of the shorts are undetectable, and many of the undetectables are easily identifiable, it appears that it is possible to reduce the likelihood, or completely eliminate, the occurrence of a large portion of these shorts by incorporating design-for-test strategies into routing software.<<ETX>>\",\"PeriodicalId\":244297,\"journal\":{\"name\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-02-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1994.326849\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1994.326849","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

无法检测到的短路可能会降低电路的长期可靠性,导致间歇性故障,增加噪声或延迟,或增加测试模式生成成本。本文描述了在ISCAS'85组合测试电路的标准单元实现中可能发生的不可检测的非反馈短路。对于每条电路的10种布局,提取相邻导线之间的所有短路,并对无法检测到的短路进行分析。我们发现,大约0.4%是无法检测到的,其中近一半可以在生成电路的物理布局之前轻松预测。由于只有一小部分短路是无法检测到的,而许多无法检测到的是很容易识别的,因此通过将为测试而设计的策略合并到路由软件中,似乎有可能减少或完全消除这些短路的大部分发生的可能性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A study of undetectable non-feedback shorts for the purpose of physical-DFT
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise or delay, or increase test pattern generation costs. This paper describes the undetectable nonfeedback shorts that are likely to occur in standard cell implementations of the ISCAS'85 combinational test circuits. For ten layouts of each circuit, all shorts between adjacent wires were extracted and the undetectable ones analyzed. We found that approximately 0.4% are undetectable and that nearly half of these can be easily predicted before the physical layout of the circuit is generated. Since only a small percentage of the shorts are undetectable, and many of the undetectables are easily identifiable, it appears that it is possible to reduce the likelihood, or completely eliminate, the occurrence of a large portion of these shorts by incorporating design-for-test strategies into routing software.<>
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