CNFET技术中基于多数逻辑的高效电流模式全加法器

Mostafa Parvizi, S. M. Ali Zanjani
{"title":"CNFET技术中基于多数逻辑的高效电流模式全加法器","authors":"Mostafa Parvizi, S. M. Ali Zanjani","doi":"10.1109/ICCKE50421.2020.9303623","DOIUrl":null,"url":null,"abstract":"In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. The proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. The simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E−17 J.","PeriodicalId":402043,"journal":{"name":"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An Efficient, Current-Mode Full-Adder Based on Majority Logic in CNFET Technology\",\"authors\":\"Mostafa Parvizi, S. M. Ali Zanjani\",\"doi\":\"10.1109/ICCKE50421.2020.9303623\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. The proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. The simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E−17 J.\",\"PeriodicalId\":402043,\"journal\":{\"name\":\"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)\",\"volume\":\"174 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCKE50421.2020.9303623\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCKE50421.2020.9303623","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

提出了一种基于多数逻辑的高速低功耗电流型全加法器(CMFA)。提出的CMFA仅由14个晶体管组成。利用HSPICE对32 nm碳纳米管场效应晶体管(CNTFET) Stanford模型进行仿真,在供电电压为0.5 V、工作频率为1 GHz、负载电容为2 fF、电流为10 μA(适用于低压高速应用的任意参考电流值)的条件下进行仿真。仿真结果表明,在最坏情况下,所提电路的和运输出延时为42 ps,功率延迟积(PDP)为98.7 E−17 J。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Efficient, Current-Mode Full-Adder Based on Majority Logic in CNFET Technology
In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. The proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. The simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E−17 J.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信