{"title":"CNFET技术中基于多数逻辑的高效电流模式全加法器","authors":"Mostafa Parvizi, S. M. Ali Zanjani","doi":"10.1109/ICCKE50421.2020.9303623","DOIUrl":null,"url":null,"abstract":"In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. The proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. The simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E−17 J.","PeriodicalId":402043,"journal":{"name":"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"174 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An Efficient, Current-Mode Full-Adder Based on Majority Logic in CNFET Technology\",\"authors\":\"Mostafa Parvizi, S. M. Ali Zanjani\",\"doi\":\"10.1109/ICCKE50421.2020.9303623\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. The proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. The simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E−17 J.\",\"PeriodicalId\":402043,\"journal\":{\"name\":\"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)\",\"volume\":\"174 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCKE50421.2020.9303623\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 10th International Conference on Computer and Knowledge Engineering (ICCKE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCKE50421.2020.9303623","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Efficient, Current-Mode Full-Adder Based on Majority Logic in CNFET Technology
In this study, a new high-speed low-power current-mode full-adder (CMFA) based on majority logic is presented. The proposed CMFA consists of only 14 transistors. Simulations are performed by HSPICE using the 32 nm carbon nanotube field-effect transistor (CNTFET) Stanford model at a supply voltage of 0.5 V, operating frequency of 1 GHz, a load capacitance of 2 fF and a current of 10 μA for any reference current value suitable for low-voltage high-speed applications. The simulation results show that, in the worst case, the delay of the proposed circuit for sum and carry outputs is equal to 42 ps, and the power-delay product (PDP) is 98.7 E−17 J.