针对Intel HARPv2 Xeon+FPGA平台的可定制矩阵乘法框架:深度学习案例研究

Duncan J. M. Moss, Krishnan Srivatsan, E. Nurvitadhi, P. Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, S. Subhaschandra, P. Leong
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引用次数: 73

摘要

通用矩阵到矩阵乘法(GEMM)是高性能计算(HPC)、科学计算(SC)以及最近的深度学习中广泛应用的基石。在这项工作中,我们为英特尔HARPv2 CPU+FPGA平台提出了一个可定制的矩阵乘法框架,该框架包括对传统单精度浮点和低精度工作负载的支持。我们的框架支持任意大小的gem,由两部分组成:(1)一个简单的应用程序编程接口(API),便于配置和集成到现有软件中;(2)一个高度可定制的硬件模板。该API提供了编译和运行时选项,用于控制硬件模板的关键方面,包括动态精确切换;交错和块大小控制;并融合了深度学习的具体操作。该框架目前支持单精度浮点(FP32), 16,8,4和2位整数和定点(INT16, INT8, INT4, INT2)以及更多用于深度学习工作负载的外来数据类型:INT16xTernary, INT8xTernary, BinaryxBinary。我们将我们的实现与最新的NVIDIA Pascal GPU进行比较,并评估内置在硬件模板中的优化所提供的性能优势。使用三个神经网络(AlexNet, VGGNet和ResNet),我们说明了降低精度表示(如二进制)可以实现最佳性能,并且HARPv2可以在Xeon和FPGA上实现细粒度的计算分区。我们观察到,与单精度浮点相比,执行时间提高了50倍,运行时配置选项可以将AlexNet中某些层的效率提高4倍,从而在整个网络中实现1.3倍的总体改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study
General Matrix to Matrix multiplication (GEMM) is the cornerstone for a wide gamut of applications in high performance computing (HPC), scientific computing (SC) and more recently, deep learning. In this work, we present a customizable matrix multiplication framework for the Intel HARPv2 CPU+FPGA platform that includes support for both traditional single precision floating point and reduced precision workloads. Our framework supports arbitrary size GEMMs and consists of two parts: (1) a simple application programming interface (API) for easy configuration and integration into existing software and (2) a highly customizable hardware template. The API provides both compile and runtime options for controlling key aspects of the hardware template including dynamic precision switching; interleaving and block size control; and fused deep learning specific operations. The framework currently supports single precision floating point (FP32), 16, 8, 4 and 2 bit Integer and Fixed Point (INT16, INT8, INT4, INT2) and more exotic data types for deep learning workloads: INT16xTernary, INT8xTernary, BinaryxBinary. We compare our implementation to the latest NVIDIA Pascal GPU and evaluate the performance benefits provided by optimizations built into the hardware template. Using three neural networks (AlexNet, VGGNet and ResNet) we illustrate that reduced precision representations such as binary achieve the best performance, and that the HARPv2 enables fine-grained partitioning of computations over both the Xeon and FPGA. We observe up to 50x improvement in execution time compared to single precision floating point, and that runtime configuration options can improve the efficiency of certain layers in AlexNet up to 4x, achieving an overall 1.3x improvement over the entire network.
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