Verification and Testing System for Local Interconnect Network Bus

In the process of Local Interconnect Network IP development and SOC design integration, it is necessary to carry out comprehensive verification test of its function and performance to ensure the functional accuracy of the module. In the process of pre-chip FPGA verification and post-chip sample verification, the commonly used verification and testing tools can only realize the normal communication test, and cannot realize the special communication test of frame time boundary and exception injection. A dedicated verification and testing system which can inject time boundary settings and error exceptions into regular communication frames was developed. The actual application test shows that the system is easy to operate and can realize the above verification and test function requirements.