以高速公路为例:fpga上嵌入式noc的设计

M. Abdelfattah, Andrew Bitar, Vaughn Betz
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引用次数: 29

摘要

我们探索了快速嵌入式片上网络(NoC)的添加,以增强FPGA现有的线路和开关,并帮助互连大型应用。FPGA结构和嵌入式NoC之间的灵活接口允许不同宽度和频率的模块通过NoC传输数据。我们研究了延迟不敏感和延迟敏感的设计风格,并提出了在嵌入式NoC上实现每种通信类型的约束。我们对图像压缩的应用案例研究表明,嵌入式NoC将频率提高了10-80%,将稀缺的长线利用率降低了40%,使设计更容易,更可预测。此外,我们利用嵌入式NoC创建可编程以太网交换机,该交换机可以在fpga上支持高达819 Gb/s的速度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Take the Highway: Design for Embedded NoCs on FPGAs
We explore the addition of a fast embedded network-on-chip (NoC) to augment the FPGA's existing wires and switches, and help interconnect large applications. A flexible interface between the FPGA fabric and the embedded NoC allows modules of varying widths and frequencies to transport data over the NoC. We study both latency-insensitive and latency-sensitive design styles and present the constraints for implementing each type of communication on the embedded NoC. Our application case study with image compression shows that an embedded NoC improves frequency by 10-80%, reduces utilization of scarce long wires by 40% and makes design easier and more predictable. Additionally, we leverage the embedded NoC in creating a programmable Ethernet switch that can support up to 819 Gb/s on FPGAs.
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