An FPGA Decision Tree Classifier to Supervise a Communication SoC

Wireless communication protocols are used in all smart devices and systems. This work is part of a proposed supervisory circuit that classifies the operation of a communication SoC, in particular, a Bluetooth (BT) SoC, at a low sampling frequency by monitoring the RF output power and input supply current. In essence, the goal is to inexpensively fabricate an RF envelope detector, power supply current monitor, and classifier on a low-cost, low-frequency integrated circuit. When the supervisory circuit detects abnormal behavior, it can shut off power to the BT chip. We extract simple descriptive features from the input and output power signals. Then, we train a machine learning (ML) model to classify the different BT operation modes, such as advertising and transmit/receive modes. In this work, we implemented the ML classifier and feature extraction on an FPGA with 100% matching with the corresponding MATLAB code. In the experimental setup, which included a function generator and an on-board ADC, errors in the FPGA-sampled values degraded the match slightly to 99.26%. Finally, a low-power ASIC is synthesized from the Verilog code in $0.18-\mu \mathrm{m}$ CMOS, with an estimated area of 0.0152 mm2 and power of $9.43 \mu \mathrm{W}$.