{"title":"SASCr2:用于立体声通信的增强硬件字符串对齐协处理器","authors":"M. Vigliar, L. Puglia, M. Fratello, G. Raiconi","doi":"10.1109/MECO.2014.6862658","DOIUrl":null,"url":null,"abstract":"In this paper new and significant improvements for a recently proposed hardware co-processor for Stereo Matching are introduced. Main focus is on small memory requirements while preserving the needed accuracy. Starting from a pair of stereo images, the co-processor computes the “disparity map” used to define corresponding points on the two images. The approach follows the well-known scheme for string alignment by Needleman & Wunsch, commonly used in bioinformatics. The architecture, highly modular, was designed by using Bluespec SystemVerilog development tool and is described in detail. Synthesis results for several FPGA platforms are shown. The actual circuit is an updated version of SASC design. Performance is benchmarked against the former implementation as well as against two reference software versions.","PeriodicalId":416168,"journal":{"name":"2014 3rd Mediterranean Conference on Embedded Computing (MECO)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"SASCr2: Enhanced hardware string alignment coprocessor for stereo correspondence\",\"authors\":\"M. Vigliar, L. Puglia, M. Fratello, G. Raiconi\",\"doi\":\"10.1109/MECO.2014.6862658\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper new and significant improvements for a recently proposed hardware co-processor for Stereo Matching are introduced. Main focus is on small memory requirements while preserving the needed accuracy. Starting from a pair of stereo images, the co-processor computes the “disparity map” used to define corresponding points on the two images. The approach follows the well-known scheme for string alignment by Needleman & Wunsch, commonly used in bioinformatics. The architecture, highly modular, was designed by using Bluespec SystemVerilog development tool and is described in detail. Synthesis results for several FPGA platforms are shown. The actual circuit is an updated version of SASC design. Performance is benchmarked against the former implementation as well as against two reference software versions.\",\"PeriodicalId\":416168,\"journal\":{\"name\":\"2014 3rd Mediterranean Conference on Embedded Computing (MECO)\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 3rd Mediterranean Conference on Embedded Computing (MECO)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MECO.2014.6862658\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 3rd Mediterranean Conference on Embedded Computing (MECO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MECO.2014.6862658","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
SASCr2: Enhanced hardware string alignment coprocessor for stereo correspondence
In this paper new and significant improvements for a recently proposed hardware co-processor for Stereo Matching are introduced. Main focus is on small memory requirements while preserving the needed accuracy. Starting from a pair of stereo images, the co-processor computes the “disparity map” used to define corresponding points on the two images. The approach follows the well-known scheme for string alignment by Needleman & Wunsch, commonly used in bioinformatics. The architecture, highly modular, was designed by using Bluespec SystemVerilog development tool and is described in detail. Synthesis results for several FPGA platforms are shown. The actual circuit is an updated version of SASC design. Performance is benchmarked against the former implementation as well as against two reference software versions.