Empirical, Analytical Study of Hardware-Based Page Swap in Hybrid Main Memory System

Emerging persistent memories (PM) such as PCM or STT-MRAM promise to make up for the shortcomings of DRAM which undergoes a scaling problem and a wasteful refresh power consumption. Hence, a future system memory is anticipated to be a hybrid of DRAM and PM. For such a system to achieve better performance, it is paramount to exploit the heterogeneity of memory access latencies with page swaps that place hot pages in faster, smaller DRAM and cold pages in slower, larger PM. The goal of this paper is to study the impact of a hardware-based page swap in a hybrid memory on the application performance. To this end, we propose a simple analytical model that evaluates the profitability of a page swap by considering a distribution ratio of memory requests between two memories and a varying access latency to each memory. By comparing the outcome of the model to the architecture simulation performance, we show that the proposed model is a useful tool to analyze the behavior of a page swap. Also, we propose and evaluate a model-guided, hardware-driven page swap mechanism which regulates page swaps online. Our experimental results show that the model appraises the profitability of a page swap with an accuracy of 90.9% for the studied workloads. Meanwhile, the model-guided page swap improves IPC performance, on average, by 28.9% and 13.3% compared to no page swap and static page swap schemes. In addition, our model-guided page swap dramatically reduces the number of page swaps by up to 17.3× over static page swap schemes, thus improving performance.