基于CAM的并行处理器的成品率和成本估算

Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1995-08-07 DOI:10.1109/MTDT.1995.518091

W. B. Noghani, I. Jalowiecki

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引用次数: 1

摘要

建立了一种综合的基于内容可寻址存储器(CAM)的联想串处理器(ASP)芯片成品率估算模型。该屈服模型包括CAM的行、列冗余策略分析和处理器结构的布局规划。最后，根据实际制造成本建立了一个成本模型，以便根据一个合适的价值值来优化处理器。

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Yield and cost estimation for a CAM based parallel processor

A comprehensive model is developed to estimate yield values for an associative string processor (ASP) chip which is populated with content addressable memory (CAM). The yield model comprises analysis of row and column redundancy strategies for the CAM combined with floor planning of the processor architecture. At the end, a cost model is developed, based on some actual fabrication costs, in order to optimise the processor according to a suitable figure of merit.

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Records of the 1995 IEEE International Workshop on Memory Technology, Design and Testing

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