纳米厚双介质薄膜(SiO/sub 2//Si/sub 3/N/sub 4/)中捕获电荷放电诱导DRAM电池信号电压的降低

J. Kumagai, K. Toita, S. Kaki, Shizuo Sawada
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引用次数: 3

摘要

研究了纳米厚SiO/sub 2//Si/sub 3/N/sub 4/双介质薄膜的陷阱/去陷阱特性及其对DRAM电池的影响。本文采用一种新的方法估算了薄膜中的净捕获电荷。圈闭/去陷阱特征强烈依赖于应力偏置。发现DRAM单元信号电压因去捕获而恶化。薄膜厚度和极板偏压的优化不仅要考虑通过SiO/sub 2//Si/sub 3/N/sub 4/薄膜的漏电流,还要考虑捕获电荷的陷阱。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reduction of signal voltage of DRAM cell induced by discharge of trapped charges in nano-meter thick dual dielectric film (SiO/sub 2//Si/sub 3/N/sub 4/)
Trap/detrap characteristics of nanometer thick SiO/sub 2//Si/sub 3/N/sub 4/ dual dielectric film and the impact of the detrapping on DRAM cell are investigated. The authors estimated net trapped charge in the film, using a new method. Trap/detrap characteristics are strongly dependent on stress bias. Deterioration of DRAM cell signal voltage due to detrapping was found. The thickness of the film and the plate bias should be optimized by considering not only leakage current through SiO/sub 2//Si/sub 3/N/sub 4/ film but also detrap of trapped charge.<>
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