smp集群的网络端点

Ilie Gabriel Tanase, G. Almási, Hanhong Xue, C. Archer
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引用次数: 5

摘要

现代大型并行机的特点是互联层次越来越深。单个处理核心采用同步多线程(SMT)来更好地利用功能单元,多个连贯处理器在一个节点中并置以更好地利用到缓存、内存和网络(SMP)的链接,多个节点通过专门的低延迟/高速网络相互连接。目前的趋势表明,未来的SMP节点将越来越宽。为了服务这些节点,现代高性能网络设备(包括Infiniband和所有IBM最近提供的产品)提供了在处理线程之间细分网络设备资源的能力。然而,系统软件在利用这些功能方面滞后,使MPI[14]、UPC[19]等用户陷入困境,需要在用户程序中使用复杂而脆弱的变通方法。在本文中,我们讨论端点的实现,端点是IBM PAMI消息库的核心软件范例[3]。PAMI端点是网络设备的一个切片的软件表达式。系统软件可以在不序列化SMP上的许多线程的情况下为端点提供服务,方法是强迫它们通过临界区。在本文中,我们描述了PAMI为程序员提供的基本保证,以及如何使用这些保证来实现高级库和编程语言(如UPC)的有效实现。我们在一个具有多达4096个内核的新型p7ih系统上评估了我们的实现效率,运行微基准测试,旨在发现点对点和集体功能的端点实现中的性能缺陷。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Network Endpoints for Clusters of SMPs
Modern large scale parallel machines feature an increasingly deep hierarchy of interconnections. Individual processing cores employ simultaneous multithreading (SMT) to better exploit functional units, multiple coherent processors are collocated in a node to better exploit links to cache, memory and network (SMP), and multiple nodes are interconnected by specialized low latency/high speed networks. Current trends indicate ever wider SMP nodes in the future. To service these nodes, modern high performance network devices (including Infiniband and all of IBM's recent offerings) offer the ability to sub-divide the network devices' resources among the processing threads. System software, however, lags in exploiting these capabilities, leaving users of e.g., MPI[14], UPC[19] in a bind, requiring complex and fragile workarounds in user programs. In this paper we discuss our implementation of endpoints, the software paradigm central to the IBM PAMI messaging library [3]. A PAMI endpoint is an expression in software of a slice of the network device. System software can service endpoints without serializing the many threads on an SMP by forcing them through a critical section. In the paper we describe the basic guarantees offered by PAMI to the programmer, and how these can be used to enable efficient implementations of high level libraries and programming languages like UPC. We evaluate the efficiency of our implementation on a novel P7IHsystem with up to 4096 cores, running micro benchmarks designed to find performance deficiencies in the endpoints implementation of both point-to-point and collective functions.
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