{"title":"一个64 MHz /spl Sigma//spl Delta/ ADC, 105 dB IM3失真，使用线性化复制采样网络","authors":"S.K. Gupta, T. Brooks, V. Fong","doi":"10.1109/ISSCC.2002.993017","DOIUrl":null,"url":null,"abstract":"The authors present a ΣΔ ADC with 105 dB distortion up to 1.5 MHz signal bandwidth, which uses a linear sampling network in a single-bit feedback 2-1-1 mash cascade modulator architecture. Operating at 64 MHz clock frequency, the measured SNR in a 1.1 MHz bandwidth is 88 dB. The area, including bypass capacitors, is 2.6 mm/sup 2/, in a 0.18 μm 1.8 V/3.3 V SP5M digital CMOS process. The power consumed is 230 mW, including references and decimation filter.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 64 MHz /spl Sigma//spl Delta/ ADC with 105 dB IM3 distortion using a linearized replica sampling network\",\"authors\":\"S.K. Gupta, T. Brooks, V. Fong\",\"doi\":\"10.1109/ISSCC.2002.993017\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors present a ΣΔ ADC with 105 dB distortion up to 1.5 MHz signal bandwidth, which uses a linear sampling network in a single-bit feedback 2-1-1 mash cascade modulator architecture. Operating at 64 MHz clock frequency, the measured SNR in a 1.1 MHz bandwidth is 88 dB. The area, including bypass capacitors, is 2.6 mm/sup 2/, in a 0.18 μm 1.8 V/3.3 V SP5M digital CMOS process. The power consumed is 230 mW, including references and decimation filter.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.993017\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.993017","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 64 MHz /spl Sigma//spl Delta/ ADC with 105 dB IM3 distortion using a linearized replica sampling network
The authors present a ΣΔ ADC with 105 dB distortion up to 1.5 MHz signal bandwidth, which uses a linear sampling network in a single-bit feedback 2-1-1 mash cascade modulator architecture. Operating at 64 MHz clock frequency, the measured SNR in a 1.1 MHz bandwidth is 88 dB. The area, including bypass capacitors, is 2.6 mm/sup 2/, in a 0.18 μm 1.8 V/3.3 V SP5M digital CMOS process. The power consumed is 230 mW, including references and decimation filter.
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