在-1模2n + 1减法中处理零

2009 3rd International Conference on Signals, Circuits and Systems (SCS) Pub Date : 2009-11-01 DOI:10.1109/ICSCS.2009.5414182

C. Efstathiou, I. Voyiatzis

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引用次数: 10

摘要

本文给出了可处理零操作数的减1操作数模2n+1减法器的高效结构。与相应的模2n+1加法器相比，所提出的减法器具有相似的架构、相同的操作速度和相同的面积复杂度。在RNS应用中，我们还提出了有效的模2n+1加/减运算符结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Handling zero in diminished-1 modulo 2n + 1 subtraction

In this work efficient architectures of modulo 2n+1 subtractors for diminished-1 operands which can handle zero operand are presented. The proposed subtractors have similar architecture, operate at the same speed and have the same area complexity compared to their corresponding modulo 2n+1 adders for diminished-1 operands. Efficient modulo 2n+1 adder/subtractor architectures for diminished-1 operands, which are welcomed in RNS applications, are also proposed.

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2009 3rd International Conference on Signals, Circuits and Systems (SCS)

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