余数发生器和多操作数模块加法器的设计

[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic Pub Date : 1991-06-26 DOI:10.1109/ARITH.1991.145540

S. Piestrak

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引用次数: 274

摘要

研究了残数发生器和多操作数模块加法器的设计。针对这两种电路，提出了采用端部进位的存进位加法器的新型高并行方案。它们是根据取模A (A是一个模)的两次幂级数的周期性推导出来的。与现有的类似电路相比，这种新型电路速度更快，使用的硬件更少

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Design of residue generators and multioperand modular adders using carry-save adders

The design of residue generators and multioperand modular adders is studied. Novel highly parallel schemes using carry-save adders with end-around carry are proposed for either type of circuit. They are derived on the basis of the periodicity of the series of powers of two taken modulo A (A is a module). The novel circuits are faster and use less hardware than existing similar circuits.<>

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[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic

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