G. Shen, V. Khilkevich, Sen Yang, D. Pommerenke, Hermann L. Aichele, D. Eichel, C. Keller
{"title":"用于ISO 10605标准的ESD抗扰度的简单D触发器行为模型","authors":"G. Shen, V. Khilkevich, Sen Yang, D. Pommerenke, Hermann L. Aichele, D. Eichel, C. Keller","doi":"10.1109/ISEMC.2014.6899015","DOIUrl":null,"url":null,"abstract":"As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.","PeriodicalId":279929,"journal":{"name":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard\",\"authors\":\"G. Shen, V. Khilkevich, Sen Yang, D. Pommerenke, Hermann L. Aichele, D. Eichel, C. Keller\",\"doi\":\"10.1109/ISEMC.2014.6899015\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.\",\"PeriodicalId\":279929,\"journal\":{\"name\":\"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISEMC.2014.6899015\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISEMC.2014.6899015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Simple D flip-flop behavioral model of ESD immunity for use in the ISO 10605 standard
As the ESD stress is becoming more and more important for integrated circuits (ICs), the ability to predict IC failures becomes critical. In this paper, an 18 MHz D flip-flop IC is characterized and its behavioral model is presented. The resulting IC model is validated in the setup according to the ISO 10605 standard. A complete model of the setup combining the IC behavioral model and the passive parts of the setup is built to estimate the failure prediction accuracy in a totally simulated environment. The results show that the model can predict the triggering level with the error of less than 20%.
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