{"title":"用于移动通信的高速锁相环频率合成器","authors":"A. Kajiwara, M. Nakagawa","doi":"10.1109/ICC.1992.268083","DOIUrl":null,"url":null,"abstract":"A novel phase locked loop (PLL) frequency synthesizer with high switching speed is proposed. The experimental and theoretical results are given. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase. Therefore, it does not need the bandlimited loop filter which limits the ability of the loop to switch rapidly. The experimental results show that it can provide a switching time as short as 0.1 ms, which is 10/sup 2/-10/sup 3/ times higher than conventional PLL synthesizers, and spurs of less than -65 dBc/Hz.<<ETX>>","PeriodicalId":170618,"journal":{"name":"[Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"High speed PLL frequency synthesizer for mobile communications\",\"authors\":\"A. Kajiwara, M. Nakagawa\",\"doi\":\"10.1109/ICC.1992.268083\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel phase locked loop (PLL) frequency synthesizer with high switching speed is proposed. The experimental and theoretical results are given. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase. Therefore, it does not need the bandlimited loop filter which limits the ability of the loop to switch rapidly. The experimental results show that it can provide a switching time as short as 0.1 ms, which is 10/sup 2/-10/sup 3/ times higher than conventional PLL synthesizers, and spurs of less than -65 dBc/Hz.<<ETX>>\",\"PeriodicalId\":170618,\"journal\":{\"name\":\"[Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICC.1992.268083\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICC.1992.268083","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High speed PLL frequency synthesizer for mobile communications
A novel phase locked loop (PLL) frequency synthesizer with high switching speed is proposed. The experimental and theoretical results are given. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase. Therefore, it does not need the bandlimited loop filter which limits the ability of the loop to switch rapidly. The experimental results show that it can provide a switching time as short as 0.1 ms, which is 10/sup 2/-10/sup 3/ times higher than conventional PLL synthesizers, and spurs of less than -65 dBc/Hz.<>