Development of a two-tap time-resolved CMOS lock-in pixel image sensor with high charge storability and low temporal noise

A high charge storability and low noise performance are both of the significant parameters for the high sensitivity time-resolved (TR) CMOS image sensors (CISs). To achieve these, we have developed the high performance TR lock-in pixel CIS embedded with two in-pixel storage-diodes (SDs). For fast charge transfer from photodiode (PD) to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large SD-FWC of approximately 7ke-, low temporal noise of 1.2e-rms at 20fps with true correlated double sampling (CDS) operation, and fast intrinsic response less than 500ps at 635nm. The proposed TR imager has an effective pixel array of 128(H)×256(V) and a pixel size of 11.2×11.2μm2. The sensor chip is fabricated by Dongbu HiTek 1-poly 4-metal 0.11-μm CIS process technology.