{"title":"采用二自由度数字分数阶PID控制器对四象限斩波馈电直流串联电机进行建模与控制","authors":"S. Khubalkar, A. Junghare, M. Aware, S. Das","doi":"10.1109/ITEC-INDIA.2017.8333876","DOIUrl":null,"url":null,"abstract":"The aim of the paper is to implement two degree of freedom digital fractional order proportional-integral-derivative (2-DOF FOPID) controller for speed control of DC series motor. Speed control is achieved by pulse width modulated control method through four quadrant chopper circuit. For realization of digital fractional order controller in integer order sense, pole-zero interlacing method is used. The controller parameters are tuned by using improved dynamic particle swarm optimization (IDPSO) technique. The effectiveness of proposed control scheme is simulated using FPGA (field programmable gate array)-in-loop wizard of MATLAB/Simulink. The performance comparison shows improvement with proposed controller as compared to integer counterpart.","PeriodicalId":312418,"journal":{"name":"2017 IEEE Transportation Electrification Conference (ITEC-India)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Modeling and control of four quadrant chopper fed DC series motor using two-degree of freedom digital fractional order PID controller\",\"authors\":\"S. Khubalkar, A. Junghare, M. Aware, S. Das\",\"doi\":\"10.1109/ITEC-INDIA.2017.8333876\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The aim of the paper is to implement two degree of freedom digital fractional order proportional-integral-derivative (2-DOF FOPID) controller for speed control of DC series motor. Speed control is achieved by pulse width modulated control method through four quadrant chopper circuit. For realization of digital fractional order controller in integer order sense, pole-zero interlacing method is used. The controller parameters are tuned by using improved dynamic particle swarm optimization (IDPSO) technique. The effectiveness of proposed control scheme is simulated using FPGA (field programmable gate array)-in-loop wizard of MATLAB/Simulink. The performance comparison shows improvement with proposed controller as compared to integer counterpart.\",\"PeriodicalId\":312418,\"journal\":{\"name\":\"2017 IEEE Transportation Electrification Conference (ITEC-India)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Transportation Electrification Conference (ITEC-India)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITEC-INDIA.2017.8333876\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Transportation Electrification Conference (ITEC-India)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITEC-INDIA.2017.8333876","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modeling and control of four quadrant chopper fed DC series motor using two-degree of freedom digital fractional order PID controller
The aim of the paper is to implement two degree of freedom digital fractional order proportional-integral-derivative (2-DOF FOPID) controller for speed control of DC series motor. Speed control is achieved by pulse width modulated control method through four quadrant chopper circuit. For realization of digital fractional order controller in integer order sense, pole-zero interlacing method is used. The controller parameters are tuned by using improved dynamic particle swarm optimization (IDPSO) technique. The effectiveness of proposed control scheme is simulated using FPGA (field programmable gate array)-in-loop wizard of MATLAB/Simulink. The performance comparison shows improvement with proposed controller as compared to integer counterpart.