{"title":"16兆字节/秒的多字母算术编码","authors":"H. Printz, P. Stubley","doi":"10.1109/DCC.1993.253137","DOIUrl":null,"url":null,"abstract":"The design and performance of a nonadaptive hardware system for data compression by arithmetic coding are presented. The alphabet of the data source is the full 256-symbol ASCII character set, plus a non-ASCII end-of-file symbol. The key ideas are the non-arithmetic representation of the current interval width, which yields improved coding efficiency in the interval width update, and the design of a circuit for the code point update, which operates at a high speed independent of the length of the code point register. On a reconfigurable coprocessor, constructed from commercially available field-programmable gate arrays and static RAM, implementation compresses its input stream at better than 16 MBytes/sec.<<ETX>>","PeriodicalId":315077,"journal":{"name":"[Proceedings] DCC `93: Data Compression Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Multialphabet arithmetic coding at 16 MBytes/sec\",\"authors\":\"H. Printz, P. Stubley\",\"doi\":\"10.1109/DCC.1993.253137\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design and performance of a nonadaptive hardware system for data compression by arithmetic coding are presented. The alphabet of the data source is the full 256-symbol ASCII character set, plus a non-ASCII end-of-file symbol. The key ideas are the non-arithmetic representation of the current interval width, which yields improved coding efficiency in the interval width update, and the design of a circuit for the code point update, which operates at a high speed independent of the length of the code point register. On a reconfigurable coprocessor, constructed from commercially available field-programmable gate arrays and static RAM, implementation compresses its input stream at better than 16 MBytes/sec.<<ETX>>\",\"PeriodicalId\":315077,\"journal\":{\"name\":\"[Proceedings] DCC `93: Data Compression Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-03-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[Proceedings] DCC `93: Data Compression Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DCC.1993.253137\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[Proceedings] DCC `93: Data Compression Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCC.1993.253137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design and performance of a nonadaptive hardware system for data compression by arithmetic coding are presented. The alphabet of the data source is the full 256-symbol ASCII character set, plus a non-ASCII end-of-file symbol. The key ideas are the non-arithmetic representation of the current interval width, which yields improved coding efficiency in the interval width update, and the design of a circuit for the code point update, which operates at a high speed independent of the length of the code point register. On a reconfigurable coprocessor, constructed from commercially available field-programmable gate arrays and static RAM, implementation compresses its input stream at better than 16 MBytes/sec.<>