{"title":"用于蓝牙的三阶连续时间σ - δ调制器","authors":"Wenjie. Yang, Wen-Hung Hsieh, C. Hung","doi":"10.1109/VDAT.2009.5158141","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a third-order continuous-time (CT) single-bit active-RC sigma-delta (ΣΔ) modulator for Bluetooth application. Through the use of the architecture, cascade of resonators with distributed feedback (CRFB), the signal bandwidth can be improved without increasing the order of the modulator. All integrators are implemented by active-RC type to have better linearity. Furthermore, in order to reduce the effect of the clock jitter, the feedback digital-to-analog converter (DAC) shape is realized by non-return-to-zero (NRZ). The modulator is designed in a standard digital 0.18µm CMOS process with a chip area of 1.32×1.23 mm2. The measurement results show that the modulator achieves 56.8dB SNDR and 60dB dynamic range over 1MHz signal bandwidth, consuming 22.2mW at 1.8V supply.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"291 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"A third-order continuous-time sigma-delta modulator for Bluetooth\",\"authors\":\"Wenjie. Yang, Wen-Hung Hsieh, C. Hung\",\"doi\":\"10.1109/VDAT.2009.5158141\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a third-order continuous-time (CT) single-bit active-RC sigma-delta (ΣΔ) modulator for Bluetooth application. Through the use of the architecture, cascade of resonators with distributed feedback (CRFB), the signal bandwidth can be improved without increasing the order of the modulator. All integrators are implemented by active-RC type to have better linearity. Furthermore, in order to reduce the effect of the clock jitter, the feedback digital-to-analog converter (DAC) shape is realized by non-return-to-zero (NRZ). The modulator is designed in a standard digital 0.18µm CMOS process with a chip area of 1.32×1.23 mm2. The measurement results show that the modulator achieves 56.8dB SNDR and 60dB dynamic range over 1MHz signal bandwidth, consuming 22.2mW at 1.8V supply.\",\"PeriodicalId\":246670,\"journal\":{\"name\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"291 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2009.5158141\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 25
摘要
本文介绍了一种用于蓝牙应用的三阶连续时间(CT)单比特有源rc sigma-delta (ΣΔ)调制器的设计。通过采用分布反馈(CRFB)谐振器级联的结构,可以在不增加调制器阶数的情况下提高信号带宽。所有积分器均采用主动rc型实现,具有较好的线性度。此外,为了减小时钟抖动的影响,采用不归零(NRZ)实现了反馈数模转换器(DAC)的形状。该调制器采用标准数字0.18 μ m CMOS工艺设计,芯片面积为1.32×1.23 mm2。测量结果表明,在1MHz信号带宽下,该调制器实现了56.8dB的SNDR和60dB的动态范围,在1.8V电源下功耗为22.2mW。
A third-order continuous-time sigma-delta modulator for Bluetooth
This paper presents the design of a third-order continuous-time (CT) single-bit active-RC sigma-delta (ΣΔ) modulator for Bluetooth application. Through the use of the architecture, cascade of resonators with distributed feedback (CRFB), the signal bandwidth can be improved without increasing the order of the modulator. All integrators are implemented by active-RC type to have better linearity. Furthermore, in order to reduce the effect of the clock jitter, the feedback digital-to-analog converter (DAC) shape is realized by non-return-to-zero (NRZ). The modulator is designed in a standard digital 0.18µm CMOS process with a chip area of 1.32×1.23 mm2. The measurement results show that the modulator achieves 56.8dB SNDR and 60dB dynamic range over 1MHz signal bandwidth, consuming 22.2mW at 1.8V supply.