蓝宝石衬底上单片集成E/D InAlN/GaN HEMT和逆变器

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2019-06-01 DOI:10.1109/EDSSC.2019.8754039

G. Gu, S. Dun, Hongyu Guo, Y. Lv, Zhirong Zhang, Zhihong Feng

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引用次数: 0

摘要

我们制作并表征了基于单片集成增强/耗尽模式(E/ d模式)InAlN/GaN高电子迁移率晶体管(HEMTs)的直接耦合场效应晶体管(FET)逻辑(DCFL)逆变器。利用低损伤的bcl3基等离子体栅极凹槽刻蚀技术实现了增强模式的InAlN/GaN HEMT，其峰值跨导(Gm)为435mS/mm，阈值电压为0.74V。当电源电压(VDD)偏置为2.5V时，E/D InAlN/GaN HEMTs逆变器的输出逻辑摆幅为2.19V，逻辑低噪声裕度为0.54V，逻辑高噪声裕度为1.38V。

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Monolithically Integrated E/D InAlN/GaN HEMT And Inverters On Sapphire Substrate

We have fabricated and characterized direct-coupled field-effect transistor (FET) logic (DCFL) Inverters based on monolithically integrated enhancement/depletion-mode (E/D-mode) InAlN/GaN high electron mobility transistors (HEMTs). The Enhancement-mode InAlN/GaN HEMT was realized by utilizing low damage BCl3-based plasma gate-recess etching, which exhibits a peak transconductance (Gm) of 435mS/mm with a threshold voltage of 0.74V. When the supply voltage (VDD) is biased at 2.5V, the E/D InAlN/GaN HEMTs inverter exhibits an output logic swing of 2.19V, a logic-low noise margin of 0.54V and a logichigh noise margin of 1.38V.

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2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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