通过双向逆向计算的节能加法

S. Wimer, A. Stanislavsky, A. Kolodny
{"title":"通过双向逆向计算的节能加法","authors":"S. Wimer, A. Stanislavsky, A. Kolodny","doi":"10.1109/EEEI.2012.6377135","DOIUrl":null,"url":null,"abstract":"This paper shows how addition can be accelerated by considering the carry as being propagating from LSB and from MSB towards a midpoint. A closed form expression for the optimal midpoint is derived. The acceleration is used to reduce the energy consumed by the adder. A 64 bit adder targeting 500MHz clock frequency, designed in 65 nanometers, consumed 18% less energy and area compared to adder generated by state-of-the-art EDA synthesis tool.","PeriodicalId":177385,"journal":{"name":"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Energy efficient addition by two-sided carry-reverse computation\",\"authors\":\"S. Wimer, A. Stanislavsky, A. Kolodny\",\"doi\":\"10.1109/EEEI.2012.6377135\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper shows how addition can be accelerated by considering the carry as being propagating from LSB and from MSB towards a midpoint. A closed form expression for the optimal midpoint is derived. The acceleration is used to reduce the energy consumed by the adder. A 64 bit adder targeting 500MHz clock frequency, designed in 65 nanometers, consumed 18% less energy and area compared to adder generated by state-of-the-art EDA synthesis tool.\",\"PeriodicalId\":177385,\"journal\":{\"name\":\"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EEEI.2012.6377135\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EEEI.2012.6377135","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

本文展示了如何通过考虑从LSB和从MSB向中点传播的进位来加速加法。导出了最优中点的封闭表达式。加速度用来减少加法器消耗的能量。针对500MHz时钟频率的64位加法器,采用65纳米设计,与最先进的EDA合成工具产生的加法器相比,消耗的能量和面积减少了18%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Energy efficient addition by two-sided carry-reverse computation
This paper shows how addition can be accelerated by considering the carry as being propagating from LSB and from MSB towards a midpoint. A closed form expression for the optimal midpoint is derived. The acceleration is used to reduce the energy consumed by the adder. A 64 bit adder targeting 500MHz clock frequency, designed in 65 nanometers, consumed 18% less energy and area compared to adder generated by state-of-the-art EDA synthesis tool.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信