用于直接射频欠采样接收机的60ghz波段S/H CMOS集成电路

Tomoyuki Furuichi, Nagahiro Yoshino, M. Motoyoshi, S. Kameda, N. Suematsu
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引用次数: 0

摘要

本文针对直接射频欠采样接收机,研制了一种60 ghz频段的采样保持电路(S/H)。在毫米波无线系统中,如IEEE 802.11ad,需要宽带特性(例如2 GHz的信道带宽)。在这种情况下,最小采样频率变为4ghz,输出缓冲放大器应至少具有2ghz带宽。该S/H-IC采用4ghz时钟对60ghz射频信号进行采样,可作为30阶欠采样接收机。由于用于2 GHz带宽输出缓冲放大器的场效应管的寄生电容与保持电容几乎相同,因此在我们的设计中可以去掉保持电容。该S/H-IC采用65nm CMOS工艺制造。该集成电路与4ghz ADC在64QAM下的信噪比为20.2 dB(通道带宽为2ghz), EVM小于5.5%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 60 GHz-band S/H CMOS IC for Direct RF Undersampling Receiver
In this paper, a 60 GHz-band Sample and Hold (S/H) IC has been developed for a direct RF undersampling receiver. In millimeter-wave wireless systems such as IEEE 802.11ad, broadband characteristic (e.g. channel bandwidth of 2 GHz) is required. In this case, the minimum sampling frequency becomes 4 GHz and output buffer amplifier should have at least 2 GHz bandwidth. This S/H-IC can sample 60 GHz RF signal by 4 GHz clock and it works as a 30th order undersampling receiver. Since the parasitic capacitance of FET used in the 2 GHz bandwidth output buffer amplifier is almost same value as the hold capacitor, the hold capacitor can be removed in our design. This S/H-IC has been fabricated in a 65nm CMOS process. The fabricated IC together with 4 GHz ADC shows SNR of 20.2 dB (channel bandwidth of 2 GHz) and EVM of less than 5.5% for 64QAM.
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