用于Sigma-Delta ADC的两级CMOS运算放大器设计

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN) Pub Date : 2016-12-01 DOI:10.1109/CICN.2016.116

Saurabh Chandra Pandey, P. Mishra, Rahul Roy, A. Pandit

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引用次数: 1

摘要

本文设计了一种用于σ - δ ADC的两级CMOS运算放大器，其工作电源为±1.8 V，采用180nm技术。这款两级CMOS运算放大器的单位增益频率为18.2MHz，增益为71.27 dB。设计与仿真部分在Cadence Custom IC CAD上完成。仿真结果令人鼓舞，具有较好的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of Two-Stage CMOS Operational Amplifier for Sigma-Delta ADC

In this paper a design of two-stage CMOS operational amplifier for sigma-delta ADC is presented, which operates at ±1.8 V power supply using 180 nm technology. This two-stage CMOS OP-AMP has been designed to indicate a unity gain frequency of 18.2MHz and indicates a gain of 71.27 dB. The design and simulation part has been done on Cadence Custom IC CAD. The simulated results are encouraging and has better performance.

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来源期刊

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)

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