An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform

This work proposes an FPGA architecture for the 1-D inverse transform of the latest video coding standard called the High Efficiency Video Coding standard (HEVC). This paper presents a new technique which computes the different sizes of the transform unit using a flexible architecture. Based on symmetrical characteristics of the elements in inverse transform matrices, the transform matrix is factorized into several matrices. This architecture supports all transform sizes i.e. 4×4, 8×8, 16×16, and 32×32. The synthesis results contributed to an operational frequency of up to 284 MHz (Altera Quartus II software) which is sufficient to encode high resolution videos in real-time.