通过将PUF响应与顺序电路的FSM交织,将硬件ip绑定到特定的FPGA设备

Jiliang Zhang, Yaping Lin, Yongqiang Lyu, R. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian
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引用次数: 6

摘要

FPGA的性能和容量的持续增长现在需要在硬件设计上投入大量资源,这导致了两类主要的安全问题:1)未经授权的使用和盗版攻击,包括克隆,逆向工程,篡改等;2)许可问题。将硬件ip (hw - ip)绑定到特定的FPGA设备可以有效地解决这些问题。然而,以前的绑定技术都是基于加密的,因此有三个主要缺点:1)加密方案在商业仅限于保护单一大型FPGA配置,2)许多加密方案依赖可信第三方涉及的许可协议,和3)加密绑定方法使用昂贵的机制如安全ROM或闪存存储FPGA具体的密钥,这是不仅昂贵而且容易边信道攻击,和密钥的管理和运输成为一个实际问题。在这项工作中,我们提出了一种完全不同于传统的基于加密的方法的PUF-FSM绑定技术来解决这些缺点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits
The continuous growth in both capability and capacity for FPGA now requires significant resources invested in the hardware design, which results in two classes of main security issues: 1) the unauthorized use and piracy attacks including cloning, reverse engineering, tampering etc. 2) the licensing issue. Binding hardware IPs (HW-IPs) to specific FPGA devices can efficiently resolve these problems. However, previous binding techniques are all based on encryption and hence have three main drawbacks: 1) encryption-based proposals in commercial are limited to protect the single large FPGA configuration, 2) many encryption-based proposals depend on a trusted third party to involve the licensing protocol, and 3) the encryption-based binding methods use costly mechanisms such as secure ROM or flash memory to store FPGA specific cryptographic keys, which is not only expensive but also vulnerable to side-channel attacks, and the management and transport of secret keys became a practical issue. In this work, we propose a PUF-FSM binding technique completely different from the traditional encryption-based methods to address these shortcomings.
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