基于0.18um CMOS输出预测逻辑的409ps 4.7 FO4 64b加法器

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.2

Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, L. McMurchie, C. Sechen

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引用次数: 9

摘要

我们提出了一种基于输出预测逻辑(OPL)的快速64b加法器，其测量的最坏情况延迟为409ps，相当于用于制造的TSMC 0.18/spl mu/m工艺的4.7 FO4逆变器延迟。这种标准化延迟比之前报道的最快的64b加法器快1.45倍。加法器使用改进的基数-3 Kogge-Stone架构，具有5个逻辑级别。

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409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

We present a fast 64b adder based on output prediction logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18/spl mu/m process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b adder. The adder uses a modified radix-3 Kogge-Stone architecture and has 5 logic levels.

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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