{"title":"具有结果共享的并发处理:模型、体系结构和性能分析","authors":"S. Krishnaprasad, B. Shirazi","doi":"10.1109/FMPC.1990.89499","DOIUrl":null,"url":null,"abstract":"An efficient computing model, called concurrent processing with result sharing, is introduced. An architecture suitable for executing programs under this model is developed. A performance analysis of this architecture based on a queuing network model is presented to investigate the effect of problem dynamics on the speed of problem solving and the resource requirements. The analysis indicates that, for both coarse- and fine-grain computations, as the amount of recomputation increases, the number of function units needed decreases and the delay at the processor element decreases significantly. For fine-grain computation, the bottlenecks at either the matching unit or the instruction store significantly degrade the system performance. This can only be avoided by using a more expensive multiple-ring architecture.<<ETX>>","PeriodicalId":193332,"journal":{"name":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","volume":"134 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Concurrent processing with result sharing: model, architecture, and performance analysis\",\"authors\":\"S. Krishnaprasad, B. Shirazi\",\"doi\":\"10.1109/FMPC.1990.89499\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An efficient computing model, called concurrent processing with result sharing, is introduced. An architecture suitable for executing programs under this model is developed. A performance analysis of this architecture based on a queuing network model is presented to investigate the effect of problem dynamics on the speed of problem solving and the resource requirements. The analysis indicates that, for both coarse- and fine-grain computations, as the amount of recomputation increases, the number of function units needed decreases and the delay at the processor element decreases significantly. For fine-grain computation, the bottlenecks at either the matching unit or the instruction store significantly degrade the system performance. This can only be avoided by using a more expensive multiple-ring architecture.<<ETX>>\",\"PeriodicalId\":193332,\"journal\":{\"name\":\"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation\",\"volume\":\"134 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-10-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FMPC.1990.89499\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1990 Proceedings] The Third Symposium on the Frontiers of Massively Parallel Computation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FMPC.1990.89499","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Concurrent processing with result sharing: model, architecture, and performance analysis
An efficient computing model, called concurrent processing with result sharing, is introduced. An architecture suitable for executing programs under this model is developed. A performance analysis of this architecture based on a queuing network model is presented to investigate the effect of problem dynamics on the speed of problem solving and the resource requirements. The analysis indicates that, for both coarse- and fine-grain computations, as the amount of recomputation increases, the number of function units needed decreases and the delay at the processor element decreases significantly. For fine-grain computation, the bottlenecks at either the matching unit or the instruction store significantly degrade the system performance. This can only be avoided by using a more expensive multiple-ring architecture.<>